A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme)

We propose and implement Stair Divided Scheme (SDS), a novel high density and low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, and thus only N/m stairs are needed in X direction for N control gates. We further present the photoresist (PR) consume model. The PR consume model fits the result well. Based on the PR consume model, we are able to prove the process efficiency and low cost of SDS. We also show that SDS can improve the integration for higher bit density. Finally, we find that the critical dimension (CD) of stair divided zone shifts post stair etching. We investigate the reason and point out that, it is necessary to make compensation in layout to ensure the precise alignment of stairs.