High-speed Comparator in 65-nm CMOS with Rail-to-rail Detection

This paper focuses on the very limited input sense level that occurs when the two input terminals of a basic latched dynamic comparator are connected to the gates of a MOSFET pair. By connecting two input pairs to the body of the MOSFET, high-speed rail-to-rail input detection is achieved, while consuming power close to that of a conventional comparator. For comparison, each comparator was redesigned in a 65-nm CMOS process and simulated at 1.0 V supply voltage. The sampling rate was carried out at 125 MHz, and as a result, it is up to 6.6 times faster than the conventional comparator in worst case delay.