A 12-bit 1.1GS/s Single-Channel Pipelined-SAR ADC with Adaptive Inter-stage Redundancy

This paper presents a 12-bit single-channel Pipelined-SAR ADC capable of operating at 1.1GS/s. An adaptive inter-stage redundancy scheme is proposed to mitigate the speed overhead caused by inter-stage redundancy bit. A new switching scheme is proposed in the first stage that largely reduces the switching power of the capacitive DAC. Implemented in a 28nm CMOS process, it achieves an SNDR of 60.1dB with power consumption of 8.5mW, corresponding to a Walden FOM of 9.3fJ/conv.-step and a Schreier FOM of 168.2dB.