可靠性(半导体)
材料科学
极紫外光刻
生产线后端
多重图案
逻辑门
电子工程
过程(计算)
光电子学
电介质
降级(电信)
计算机科学
图层(电子)
可靠性工程
抵抗
纳米技术
功率(物理)
工程类
物理
量子力学
操作系统
作者
Chanhoo Park,Minkwon Choi,Changhyun Kim,Bonjae Koo,O. Young Kweon,Jung O. Park,Juyoung Jung,Young Cheol Choi,Kyoung-Woo Lee,Jeong Hoon Ahn,Ja-Hum Ku
标识
DOI:10.1109/iitc/mam57687.2023.10154737
摘要
This paper describes two advanced technologies recently adopted in back-end-of-line (BEOL) process for our logic products: self-aligned-universal-patterning (SAUP) and sacrificial oxide layer (SOL). Advantages of SAUP include improved extreme ultraviolet (EUV) throughput, reduced pinch-off type patterning defects, improved reliability, and lower power rail resistance. SOL is found to be an effective means to avoid dielectric damage and resulting RC degradation occurred by multiple etch processes.
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