功勋
电容器
电容
逐次逼近ADC
噪音(视频)
偏压
稳健性(进化)
采样(信号处理)
物理
电子工程
电气工程
计算机科学
电压
光电子学
工程类
探测器
光学
电极
化学
人工智能
生物化学
量子力学
图像(数学)
基因
作者
Mingtao Zhan,Jie Lü,Xiyuan Tang,Yi Zhong,Nan Sun
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2024-01-01
卷期号:: 1-10
被引量:1
标识
DOI:10.1109/jssc.2023.3344461
摘要
This article presents a compact 13-bit 200-MS/s pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) with a robust current-biased ring amplifier (ring-amp) and kT/C noise cancellation. The proposed current-biasing scheme using split capacitors significantly enhances the PVT robustness of the ring-amp. With additional split capacitors used for current-biasing, the kT/C noise cancellation technique can be seamlessly implemented in this architecture. With kT/C noise cancellation, the input-referred thermal noise can break the input sampling kT/C noise limit. As a result, the input sampling capacitance can be greatly reduced. With only 128-fF single-end input sampling capacitance, the prototype ADC implemented in a 28-nm process achieves 67-dB SNDR with only 0.004-mm $^2$ core area. The power consumption at 200 MS/s is 1.3 mW, yielding a Schreier figure of merit of 175.5 dB and a Walden figure of merit of 3.7 fJ/conversion-step.
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