Influence of crystal-originated pits on ultra-thin gate oxides

The impact of the crystal-originated pits (COP) on thick gate oxides within the 200-1000A range has been clearly demonstrated throughout the last two decades as a degradation in the oxide electrical breakdown. With the ever-decreasing gate oxide thickness in advanced CMOS (sub-0.20μm feature size) process technology, the detrimental influence of the silicon pits on ultra-thin oxides has been minimal. However, the substrate effect can be shown by using the diagnostic defect inspection station with the referenced SEM defect review. The COP defects can be compared to the electrical tests, which pinpoint the electrical defects by photo detection of the breakdown points. The variation of substrate conditions with different defect sizes and densities on ultra-thin oxides indicate that the silicon pit effect is gradually improving with thinner oxides. The gate oxide integrity (GOI) is a function of the pit structure and dielectric film thickness uniformity inside the pit.