Small Package Size Low Power CMOS Image Sensor using Two Different Type Small Through Silicon Vias Technology for 3D Packaging

This paper is to address how to change the image ball grid array (iBGA) design to image chip scale package (iCSP) design with a minimal design effort in order to reduce package size and dynamic power consumption. We have introduced our new advanced small diameter Through Silicon Via (TSV) technology into sensor to connect power instead of the traditional wire bond. We have kept using backside via stack (BVS) technology to interconnect an upper active pixel sensor (APS) array die and a lower image signal processor (ISP) die for 3D packaging. The additional different type TSV technology enables for the bottom ISP die to directly connect to the digital power without passing through the top APS array die. As a result, ISP die of our new product could perform high-end digital functionalities under the even smaller resistance stable power supply network due to BVS and TSV fabrication process. Power network implementations of iBGA and iCSP have been compared in terms of vectored static power analysis. Our new combination helps the feasible lowest operating voltage of ISP die to be lower than the packaging combination of BVS and wire bond. It consequently would lead to power saving of high-end image sensor for mobile devices.