A study of STI stress impact on DC performance of nano-scale NMOS

This work investigates the impact of STIW (the width of shallow-trench-isolation) on DC behavior of nano-scale device. Based on theoretical analysis, several devices with different STIW and fingers based on 65nm CMOS process were designed. The test results prove that it is very important to consider the influence of STIW especially for threshold voltage model of nano-scale device with one finger.