逻辑电平
电气工程
NMOS逻辑
电子工程
电压
低压
传播延迟
计算机科学
晶体管
工程类
作者
Ahmed A Abdelmoaty,Mohammad A. Al-Shyoukh,Ayman Fayed
标识
DOI:10.1109/apec.2016.7468207
摘要
A level-shifting circuit with sub-nano-second propagation delay for high input voltage switched-mode power converters is presented. The proposed circuit uses isolated low-voltage NMOS transistors and capacitive coupling to shift the control signal of the high-side power switch from a low-voltage logic domain (VLogic ~ 5V) up to a high-voltage power domain (VIN ~ 65V) with less than 115ps propagation delay. As a result, the non-overlap time inserted between the control signals of the high-side and low-side power switches can be minimized, leading to higher efficiency. Moreover, the control signal is shifted to the high-voltage power domain without reducing its voltage swing, which helps minimizing the on-resistance of the switch and further improves efficiency. The proposed circuit is fully integrated in a 0.18μm technology with no off-chip components. It occupies less than 0.75mm2 and provides built-in protection for the low-voltage devices with no additional protection circuitry. Transistor level simulations demonstrate the circuit's functionality and performance.
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