A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

Abstract Silicon‐on‐insulator junctionless transistor (SOI‐JLT) is introduced as an efficient device for nanoscale destinations. Moreover, critical lattice temperature and high leakage current are taken into account as the fundamental challenges can limit the use of the SOI‐JLTs. This paper aims to modify a conventional junctionless in order to improve the electrical and thermal performance. A new window filled by lightly doped P‐type silicon material opens inside a part of the buried oxide beneath the channel region. This reformation in the junctionless creates a depletion layer at the channel region/new window interface to reduce the leakage current, successfully. Also, the critical lattice temperature of the proposed structure will be mitigated owing to higher effective thermal conduction in contrast to the conventional SOI‐JLT structure. Two carriers and two‐dimensional (2D) simulation of the structures under the study considering the various spectra of parameters in terms of lattice temperature, leakage current, electron temperature, driving current, transconductance, output conductance, parasitic capacitance, current gain, unilateral power gain, cutoff frequency, maximum oscillation frequency, and minimum noise figure revealed that the suggested device provides a better opportunity for the researchers and experimentalists to implement and develop it for VLSI applications.