Novel RDL Design of Wafer-Level Packaging for Signal/Power Integrity in LPDDR4 Application

The emerging wafer-level packaging (WLP) technology suffers from serious signal integrity (SI) and power integrity (PI) issues due to its redistribution layer (RDL). There exhibit serious parasitic effects by the high-density RDL traces and less flexibility of decoupling capacitors, so the robust power distribution network is critical to design. This paper proposed a novel two-layered RDL design in low-power double data rate fourth generation (LPDDR4) application by proposing a novel power/ground meshed layout for superior PI performance. Besides, the second-order RLC simplified model and normalized resistance are derived to handle the process scaling issue for successful SI by adjusting the cross-sectional structure of RDL so that LPDDR4 4266 can work well on 2-μm WLP.