27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS

In recent years, the operation speed of SAR ADCs has improved with the scaling of CMOS technology. SAR ADCs achieve a few hundreds of MS/s with 8-to-10b resolution. The SNR of high-speed SAR ADCs is mainly dominated by comparator noise and usually limited to 50 to 60dB. The power consumption increases exponentially to suppress comparator noise in a limited comparison time to improve SNR. Noise-tolerant SAR ADCs [1] reduce comparator power in the first few bit cycles by using a coarse comparator. However, the fine comparator in the remaining bit cycles still consumes significant power to achieve an SNR greater than 60dB. SAR-assisted pipelined ADCs [2,3] do not require a low-noise comparator, but design restrictions in advanced CMOS processes make high-performance amplifier design challenging. Using a low-gain or a dynamic amplifier induces gain errors between stages. Besides, the amplifier and back-end stages result in extra noise and area. Digital-slope ADCs [4] are inherently low-noise by quantizing the signal in the time domain, but the hardware cost grows exponentially with resolution and the maximum conversion rate is halved with each additional bit of resolution. Hence this ADC type is unattractive for resolutions higher than 8b. This paper reports a 12b hybrid ADC combining a 7b low-power SAR coarse ADC with a 6b low-noise digital-slope fine ADC. The 100MS/s ADC achieves 64.43dB SNDR at Nyquist input with 0.35mW from a 0.9V supply.