Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis

Memory level parallelism (MLP), which refers to the number of memory requests concurrently held by Miss Status Handling Registers (MSHRs), is an indispensable factor to estimate cache performance. Unfortunately, due to the complexity of obtaining the maximum number of memory instructions or cache misses among all dependence paths, previous works in MLP modeling are very time-consuming in trace profiling. In this paper, we propose a fast model for evaluating MLP without analyzing all dependence paths in the instruction windows. Instead, we construct a probability model to estimate the maximum number of cache misses among all dependence paths in the instruction windows fed with some easily obtained inputs. By doing so, we greatly reduce the time overhead of the MLP model with a slight drop in accuracy. Twelve benchmarks chosen from Spec2006 are adopted for evaluating the accuracy and time overhead of our model. The average error of our model compared with the results of Gem5 simulations is around 9%, while the time overhead of the MLP evaluation process can be decreased to about half of previous models.