Kick-back Noise Reduction and Offset Cancellation Technique for Dynamic Latch Comparator

In this work, a novel kickback noise reduction technique is represented. This method aims to reduce both common-mode and differential-mode components of kickback noise in the dynamic latch comparator. This method reduces maximum kickback noise current by more than %68. Also, we use a body voltage trimming calibration scheme to reduce offset from 13.2 $\text{mV}$ to ${\sim 0.3}\text{mV}$ efficiently. This dynamic comparator is simulated in 0.18 ${\mu}\mathrm{m}$ CMOS technology, which consumes 2.86 ${\mu} \mathrm{W}$ in each comparison cycle. So it is appropriate for low-power applications.