A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator

A 10 Gb/s clock and data recovery (CDR) circuit for use in multi-channel applications is presented. The module comprises a binary phase detector, an analog phase interpolator, and a 1:4 demultiplexer. The prototype macro fabricated in a 0.11 /spl mu/m CMOS technology consumes 220 mW. The active area is about 0.25/spl times/1.4 mm/sup 2/. The CDR fulfills the jitter tolerance requirements set by SDH/SONET with the test being based on a BER of 10/sup -12/ and a PRBS of 2/sup 23/-1.