(Keynote) FDSOI Past, Present and Future

FDSOI is quickly becoming a technology offering that can deliver next generation performance with superior low power operation at a significant cost advantage. Researchers have actively pursued alternatives to conventional bulk and PDSOI transistors for well over 10 years. However, there was not enough compelling need to change until conventional CMOS scaling dramatically slowed. Beyond the 28nm node new device architectures were needed to continue the scaling trend. FDSOI was always thought to be an attractive option since of all the alternative approaches it is the most similar to conventional bulk or PDSOI. This is mainly due to the fact that it is planar and thus much of the process and design methodology can be re used from previous nodes. On the other hand several key issues for FDSOI were known and thought to be fundamental challenges. Specifically silicon consumption, high external resistance and parasitic capacitance were identified as major hurdles. FDSOI relies upon the thin channel to control short channel effects. For example a channel thickness of approximately 6nm is required to maintain good electrostatics for a transistor with Lg=20nm. Maintaining thin silicon in the channel while still preserving silicon in the source-drain regions is a big process challenge. We have carefully optimized several key process steps including the spacer etch process to eliminate excessive silicon consumption. As shown in Fig. 1 the zero loss spacer process features a partial etch using reactive ion etching. In order to minimize silicon consumption, the spacer etch is terminated before the spacer material is completely removed from the horizontal surfaces and the dry etch cannot consume silicon. The residual spacer material is removed as part of the pre epi clean for raised source-drain. Since the wet etch for the pre-clean is highly selective to the silicon, there is no silicon consumption. High external resistance was thought to be a significant challenge for FDSOI mainly in part due to the silicon consumption from the spacer process but also from the junction formation process. Ion implantation is well known to cause damage in thin silicon even with high temperature activation anneal. The silicon damage caused by the ion implantation can also cause defective epitaxial growth during the raised source drain process. We have solved the challenge of junction formation for FDSOI by developing an implant last scheme. After the spacer module is completed the raised-source and drain is formed. Since the ion implant is done into the thick raised-source drain, the damage created is healed during the activation anneal. Parasitic capacitance is another known issue for devices with raised-source drain. We have developed a facetted epi process which eliminates a significant component of the additional parasitic capacitance caused by the raised-source drain (Fig. 2). 1 We have also developed several key elements that enable high performance FDSOI circuits. In-situ doped SiGeB for raised source-drain has been developed to reduce contact resistance and form abrupt junctions for pFETs. SiGe channel is another innovation we have developed to enable high performance by increasing hole mobility. Fig. 3 shows the benefit of the strained SiGe raised source-drain and the SiGe channel. 2 FDSOI is scalable and can be used for several technology nodes. Gate length scaling for FDSOI can be accomplished by thinning the silicon. Reverse back bias can also be used to improve short channel effects and enable scaling. Figure 4 shows the improvement in short channel control as the silicon is thinned down to 3.5nm Remarkably the external resistance of the devices is not compromised as evidenced by the Ion vs Ioff comparison to devices with 6nm channel thickness. The same figure also shows the improvement in electrostatic behavior with reverse back bias. 3 Additional improvements in FDSOI performance can be achieved by strained silicon on insulator technology. Figure 5 shows the benefit of the strained silicon channel for nFETs. 4 Table 1 shows a comparison of state of the art FDSOI research transistors to FinFETs. 5 It is interesting to note that the FDSOI devices can achieve competitive drive currents at dramatically shorter gate-lengths thereby improving circuit performance. It is also interesting to note the FinFETs are normalized to the footprint which is 30% greater than the effective channel width. References K. Cheng et. al. IEDM 2010. K. Cheng et. al. IEDM 2013. A. Khakifirooz et. al. EDL 2012. A. Khakifirooz et. al. VLSI 2012. Q. Liu et. al. IEDM 2014. Figure 1