调试
追踪
静电放电
计算机科学
直线(几何图形)
根本原因
过程(计算)
CMOS芯片
根本原因分析
晶体管
嵌入式系统
印刷电路板
可靠性工程
工程类
电子工程
电气工程
操作系统
电压
几何学
数学
作者
Yossi Shoshany,Harshit Dhakad,Wolfgang Stadler,Muhammad Azamuddin Aminuddin,Ethan How Chen Wong,Norhafizah Mohd Rasdi,Wooi Teong Tan,Ginger Jiang,Sharon Huang,Shahar Wolf,Ina Shternberg,D. Racah,Sui Minh Khaw,Khai Chee Hong,Yen Nee Lim
标识
DOI:10.23919/eos/esd54763.2022.9928498
摘要
A functional failure of a connectivity module is investigated and traced down to transistor level in the CMOS IC. The presentation discusses failure analysis, layout inspection, ESD simulations, experiments to validate and understand the root cause, and process assessment in the assembly line. The analysis identified a charged board event.
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