Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology

In this work, a multiple-Vt solution with a Vt range of -200mV and a tight Vt distribution is demonstrated to enable the design flexibility for a 3nm CMOS technology. This is achieved by characterizing and reducing the gate-related layout dependent effects and the gate resistance at scaled cell height and gate length to meet the Vt requirements without compromising the device performance through careful metal gate stack optimization enabled by inserting a passivation layer on thin, low-resistivity work function metal.