Effect of Solder Voids on Chip Crack during Al Ribbon Bonding

Demand for high power packages in the market is currently increasing especially in automotive field where more manufacturers are developing autonomous driving system and electric vehicle. Therefore, high power package design is becoming crucial. One of the critical parts in high power package design is the power interconnect where the chip interconnect must be able to carry high current but must be electrically and thermally low resistance. Infineon Technologies AG, developed the Al ribbon bonding for their high-power packages in their largest manufacturing site in Melaka. During the development, chip crack was observed in one of the packages after the ribbon bonding process. This paper aims to investigate the mechanism behind the bond pad deformation and the effect of solder voids on the risk of chip cracking during Al ribbon bonding. In this study, we focus on the Al ribbon bond and its interaction with the chip as interconnect. The investigation is carried out using simulation by Finite Element Method and then validated by physical experimentations. The Al ribbon bonding process is simulated with actual wire bond parameters. The solder voids in the die attach layer is modeled explicitly to capture the effect of the solder on the pad deformation and chip stress. The abnormal pad deformation was observed in the simulation model with a single small solder void directly under the bonding area. The chip which is attached to the solder takes on the same deformation resulting in abnormal pad deformation which we observed after the ribbon bond was etched away. The size of the void in the solder layer is increase to investigate the effect of void size on the pad deformation. Simulation results of the bond pad deformation show good trend correlation with actual sample builds. The correlation between simulation results and actual measurements provided a clear understanding of the failure mechanism thus, identifying the solder voids as the root cause.