7.9 An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process

In CDR, to sample time-interleaved ADCs with 4-phase inputs, the utilization of local clock generators including phase interpolators (PI) with high precision is imperative to eliminate phase offsets and prevent spurs at the ADC output. This necessitates either the parallel operation of two PIs with differential quad inputs driven by a DLL or the addition of an extra quad-generator at the 2-phase PI output, resulting in increased power consumption (Fig. 7.9.1). Similarly, baseband beamforming systems [1] for large-antenna arrays with wide signal bandwidth also require high-speed, linear, and fine-resolution PI for each antenna to compensate for the delay mismatch, while maintaining low power consumption (Fig. 7.9.1). This work proposes a low-power PI with power efficiency of 0.18mW/GHz implemented in 65nm CMOS with the capability to directly generate 4-phase PI outputs at clock frequencies of up to 6GHz without any DLL or quad generator at the input side suitable for CDR applications and 2-phase PI outputs of up to 12GHz.