Beyond 20nm DRAM Capacitor Etch Challenge and Process Solution

With the smaller size of the dynamic random access memory, the capacitor etch becomes more and more difficult due to the smaller critical dimension (CD) and higher aspect ratio. We found that mask selectivity, CD control, missing holes and bottom distortion will become very margin when capacitor aspect ratio is higher than 30. To address the challenges, we propose some process solutions in three directions, including lower pressure, higher bias power with low duty cycle and new chemistry are all effective to etch very small and deep capacitor holes. We also try to explain the mechanism of observed performance caused by optimal process conditions. It will be a good reference of capacitor etch for the next generation of DRAM.