Methodology for CNN Implementation in FPGA-Based Embedded Systems

The increasing interest in convolutional neural networks (CNNs) is driving the study and design of different implementations for a variety of platforms, each intended to optimize performance, power consumption, or latency, according to the application's needs. While GPUs have dominated the high-performance terrain, FPGAs have proved to be a promising alternative due to their relatively high performance and reduced power consumption and costs, compared with GPUs. The main concern regarding FPGA implementations lies in the effort needed to develop the systems and difficulties reusing or combining designs by different authors, due to the highly heterogeneous architectures used in each project. This work proposes a methodology and a high-level architecture designed for CNN implementations in FPGAs, which eases the development process, allows the reusability of designs, and helps to maximize performance, minimize latency, reduce resource utilization, and avoid possible bottlenecks, while allowing high design flexibility. This proposal is validated by implementing a set of blocks that are later used to build different CNNs.