A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity

This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5 $\text{m}\text {V}_{\text {pp}}$ differential input ( $\Delta V_{\textrm {I}}$ ) at 0.5 V common-mode ( $V_{\textrm {CM}}$ ) and 1V supply ( $V_{\textrm {DD}}$ ). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a < 70ps delay down to 0.6 V $V_{\textrm {DD}}$ . The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution.