薄脆饼
可靠性(半导体)
晶圆规模集成
面子(社会学概念)
比例(比率)
材料科学
晶圆级封装
光电子学
计算机科学
物理
社会科学
功率(物理)
量子力学
社会学
作者
M. Haneda,Yukako Ikegami,Kengo Kotoo,Kan Shimizu,Y. Kagawa,Hayato Iwamoto
标识
DOI:10.1109/ectc51529.2024.00218
摘要
Wafer-on-wafer-on-wafer integration, consisting of three device wafers, is a key concept that accelerates the evolution of stacked devices. We have successfully developed Wafer-On-Wafer-On-Wafer integration technologies which consist of 1 μm pitch Face-To-Face and Face-To-Back Cu-Cu connections and 6 μm pitch TSVs processes having large-scale of 50,000 links, good connectivity, and high reliabilities for the first time. Nicely aligned and bonded Cu pads are observed at Face-To-Face and Face-To-Back bonding each interface. Each connectivity of the 3D components: Face-To-Face, Face-To-Back Cu-Cu connections and TSVs, was quantitatively discussed with electrical resistance data. The TSVs proximity effects in Wafer-on-wafer-on-wafer integration were investigated by employing silicon resistor formed on the middle wafer frontside to discuss the effect of Face-To-Back Cu-Cu hybrid bonding.
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