示意图
电子工程
输电线路
静电放电
信号边缘
薄脆饼
计算机科学
电子线路
栅氧化层
工程类
电压
电气工程
晶体管
数字信号处理
模拟信号
作者
Umair Ishfaq,K. Domański,Susanne Heber,Harald Goßner
标识
DOI:10.23919/eos/esd54763.2022.9928517
摘要
A Charged Device Model (CDM) simulation method has been demonstrated to predict CDM fail current of receiving circuits with gate oxide connected to pad. This method involves inclusion of 20ps rise time edge into the stimulus. It was shown previously that this fast rise time component of the pulse can cause the gate oxide damage. The simulation method is intended as a schematic-level tool during pre-silicon design phase to deliver CDM ESD protection. Simulation results are verified by silicon results with qualification CDM test on package and Transmission-Line-Pulse (TLP) measurements on wafer-level.
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