Symmetric Reconfigurable Ferroelectric Transistor for Non-Volatile Memories to Diminish the Effects of Gate Leakage

Reconfigurable ferroelectric transistor (R-FEFET) is a variant of a ferroelectric transistor (FEFET), which utilizes two asymmetrically sized gate stacks to achieve voltage-controlled modulation in hysteresis and dynamic reconfigurability between volatile and non-volatile modes. However, due to a floating internal metal layer (IML), gate leakage (GL) can lead to a polarization-dependent shift in device characteristics over time. This degrades read disturb margins (RDM) and the non-volatile memory (NVM) robustness. In this work, we propose an R-FEFET with symmetric gate stacks to diminish the adverse effects of GL on NVM operation. Utilizing our new R-FEFET, we propose a two-transistor NVM (2T-R), which exhibits up to 12% higher energy efficiency, $3\times $ increase in the RDM, and 14% lower area compared to an existing R-FEFET NVM. We also perform variation analysis showing a robust operation of the symmetric R-FEFET NVM.