A Reference Current Source with Cascaded Nagata Current Mirrors Insensitive to Supply Voltage and Temperature

This paper investigates a supply voltage and temperature insensitive CMOS current reference with cascaded Nagata current mirrors. The Nagata current mirror has a peak with respect to its input current, and the current change rate is small in the vicinity of the peak. By the cascade structure design, the output current can be insensitive to a wide range of supply voltage. Further, we show here that its temperature insensitivity is realized by biasing the gate-source voltage at the zero temperature coefficient condition for the drain current. The investigated circuit is designed using TSMC 180nm CMOS process with 3.3 V supply voltage. Our LTspice simulation shows that it achieves a 4μA current with temperature variation of less than 3% or 180ppm/°C over the range of -45°C to 95°C with simple configuration.