Design and implementation of high speed reconfigurable NoC router

In this paper, a high speed reconfigurable router has been designed and implemented. The proposed reconfigurable router the buffer slots are dynamically allocated which in turn increases the efficiency of the network with heavy loads. In the proposed router the depth of each buffer used in the inputs can be reconfigured at design time. The dynamic power consumption of the router is 5mW. Area and frequency analysis have been done. Also timing constraint has been improved making the router high speed reconfigurable router.