背板
收发机
CMOS芯片
计算机科学
发射机
宽带
电子工程
计算机硬件
频道(广播)
嵌入式系统
工程类
电信
作者
Jafar Savoj,Kenny Hsieh,Parag Upadhyaya,Fu-Tai An,Ade Bekele,Stanley Chen,Xuewen Jiang,Kang Wei Lai,Chi Fung Poon,Aman Sewani,Didem Turker,Karthik Venna,Daniel Wu,Bruce Xu,Elad Alon,Ken Chang
标识
DOI:10.1109/vlsic.2012.6243811
摘要
This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA. The receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation. A 5-tap speculative DFE removes the immediate post-cursor ISI. Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm. A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation. The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation. The transceiver achieves BER <; 10 -15 over a 33dB-loss backplane at 12.5Gb/s and over channels with 10G-KR characteristics at 10.3125Gb/s.
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