随时间变化的栅氧化层击穿
可靠性(半导体)
电迁移
互连
生产线后端
材料科学
CMOS芯片
可靠性工程
节点(物理)
制作
介电强度
压力(语言学)
过程集成
电介质
过程(计算)
电子工程
计算机科学
光电子学
电气工程
工程类
栅极电介质
晶体管
工艺工程
电压
复合材料
功率(物理)
操作系统
物理
医学
量子力学
病理
结构工程
语言学
计算机网络
替代医学
哲学
作者
F. Chen,B. Li,Tae‐Gon Lee,C. Christiansen,J. Gill,M. Angyal,M. Shinosky,Chad Burke,W. Hasting,R. Austin,T. Sullivan,D. Badami,J. Aitken
标识
DOI:10.1109/ipfa.2006.251007
摘要
During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for 65nm Cu/low-k interconnects is reported and various reliability issues associated with process integration and material optimization during initial development stage are discussed. Finally, we demonstrate that with careful process and materials optimization, a superior interconnect reliability performance at the 65nm technology node can be achieved for 300mm fabrication. The projected reliability lifetimes of TDDB, EM, and SM meet the most stringent reliability targets and criteria
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