A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter

Digital PLLs (DPLLs) have demonstrated to be a promising candidate to implement frequency synthesizers in wireless transceivers, thanks to their scaling-friendly architecture and to the possibility of implementing powerful background adaptive calibration algorithms to compensate the system non-idealities. The combination of these features leads to an inherently faster time-to-market than traditional analog PLLs, avoiding lengthy porting and redesign phases and factory calibrations, making DPLLs particularly attractive to cope with the surge of mobile applications recently driven by remote working and contactless businesses. Among DPLLs, bang-bang DPLLs are especially attractive for their reduced complexity and low power consumption, thanks to the use of a binary phase detector (BPD), while still capable of achieving state-of-the-art phase noise, jitter, and fast-lock performances [1]–[2]. However, the DPLL bandwidth, on top of being subject to process, voltage, and temperature (PVT) variations, also depends on the system phase noise level [3].