Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs

With the growth of high-speed computing memory, the HBM (High Bandwidth Memory) has been developed using advanced process technologies including high-k and metal gate process for the interfacing logic chip and 3D DRAM stack structures with TSV connections. This paper reviews overall reliability of the advanced HBM with 17nm DRAM process from device level to product level. This includes the product aging focused on logic buffer die and environmental reliability of the integrated multi-layer structure. Intrinsic FEOL and BEOL reliability such as TDDB, NBTI and EM were demonstrated >10 years of lifetime. Ni/Cu UBM (Under Bump Material) improved EM lifetime by $\boldsymbol{15\mathrm{x}}$ compared to the previous Ni UBM. In addition, a novel package test method considering mechanical stress on 2.5D SiP (silicon in package) enabled the interconnect reliability including TSV/micro bump EM and package environmental tests level to be evaluated more precisely. Reliability of HBM with 17nm high-k metal gate process showed robustness and meets 10yrs lifetime with HTOL over 1000hrs aging, hot temperature storage, temperature humidity bias and precondition including multiple cycles of IR reflow for production.