Silicon Surface Passivation by Thin Thermal Oxide/PECVD Layer Stack Systems

For the passivation of p-type silicon surfaces, we investigate layer systems consisting of a thin layer of thermally grown SiO ₂ and different dielectric capping layers deposited by means of plasma-enhanced chemical vapor deposition (PECVD). We find that the thermal SiO ₂ layer thickness strongly impacts the passivation quality and interface parameters of the stacks. Capacitance-voltage measurements reveal that for Al ₂ O ₃ and SiN x capping layers, an increased thermal SiO ₂ film thickness suppresses charge formation at the interface between SiO ₂ and the capping layer. Interface trap density and effective carrier lifetime data suggest that a certain thermal SiO ₂ thickness is required to achieve appropriate chemical passivation. The combination of a thin thermal SiO ₂ layer (~4 nm) and a PECVD-SiO x capping results in very low surface recombination velocities of a few centimeters per second, measured on p-type 1-Ω·cm float-zone silicon after contact firing and postmetallization annealing. The experimentally observed dependence of the surface recombination velocity on the fixed charge density, gate voltage, and injection density is reproduced very accurately by analytical calculations that use the measured interface trap density and total charge density at the Si/insulator interface. The model also includes additional recombination in the space charge region of inverted surfaces.