Graphoepitaxially Side‐By‐Side Nanofins Along Atomic Terraces for Enhancement‐Mode FinFETs with 108 On/Off Ratio

Abstract The innovation of 3D FinFETs using top‐down silicon nanofins represents a significant advancement toward scaling down microchip process nodes to the cutting‐edge 3‐nm level. While bottom‐up semiconductor nanofins also hold promise as building blocks for FinFETs, their controlled growth remains challenging. Drawing inspiration from the guided roots along brick gaps, this study shows that the aligned atomic terraces on an annealed miscut LaAlO 3 surface can trigger an exceptional graphoepitaxial effect, encouraging the bottom‐up vapor‐phase growth of self‐aligned nanostructures such as CdS, CdSe, ZnSe, and ZnTe. Subsequently, the resultant CdS nanofins, characterized by narrow widths of ≈20 nm and large height‐to‐width ratios exceeding 16, can be seamlessly assembled into arrayed FinFETs on the insulating LaAlO 3 substrate, obviating the need for post‐growth alignment steps. Unlike most nanostructure‐based planar transistors, which often operate in depletion mode characterized by negative thresholds, these FinFETs operate in enhancement mode with positive thresholds (≈5 V), ≈10 −14 ‐A standby currents, and ≈10 8 on/off current ratios. The achieved ratio surpasses the record for planar enhancement‐mode CdS transistors by 4 orders of magnitude, primarily due to the enhanced electrostatic control over the nanofins. Overall, the graphoepitaxially side‐by‐side nanofins show tremendous potential to expand the repertoire of FinFETs based on non‐silicon semiconductors.