Embedded Microchannel Cooling for the System on Wafer Packaging

The system on wafer (SoW) packaging is borne out of an opportunity that the chip manufacturing process iterated to the nanoscale and Moore's Law was no longer economically viable. The SoW mode can bypass advanced manufacturing process nodes, which is implemented by fabricating different functional partitions of a system on a chip (SoC) into some separate chiplets, then combining these chiplets in a way similar to building blocks through advanced packaging techniques. High heat accumulation caused by the high-density integration of multiple chips and wiring signals in silicon-based wafers will pose considerable problems for the warpage of the wafer. Therefore, the simulation study was performed on the thermal performance of embedded microchannel heat sinks for the SoW packaging. This work mainly focused on the investigations of the effects of the geometric parameters of the microchannels on the cooling performance of SoW. The simulation results show that the inlet flow rate influences the thermal resistance and pressure drop of SoW more greatly than the width of the microchannel in the straight and parallel design. Simulations also suggest that the hydraulic and heat transfer performance of embedded manifold microchannel heat sinks are the best-in-class compared to the straight and parallel microchannel and double spiral microchannel heat sinks, which will contribute to a high-density integration of chiplets and more flexible SoW packaging.