The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs

In this work, we discuss the influence of strained silicon technology on transistors in the context of Through Silicon Via (TSV) thermal stress. An accurate thermal stress distribution around a single TSV is firstly obtained by finite element analysis. Then we simulate the transistors using strained silicon technology and apply the TSV–induced stress to the structure to study their magnitudes and mutual influences. We demonstrate that the combined stress distribution of these two stress sources in 45 nm planar transistor cases can almost be viewed as the superposition of each individual distribution results. While in complex 3D structures like the case of FinFETs or the case considering 3D structures in dies, the TSV stress has little impact. Based on the updated stress distribution, the carrier mobility variations of the channels of planar transistors around the TSV are studied. In our experimental setup, the mobility of PMOS is weakened in the x-axis and enhanced in the y-axis, while NMOS has an opposite feature. Besides, the strained silicon technology can greatly enhance the carrier mobility. Finally, we discuss the determination of the keep out zone of a TSV in circuit design based on the aforementioned performance variations of transistors.