A 0.4–6 GHz Receiver for Cellular and WiFi Applications

A wideband RF receiver employs a multi-loop architecture to ease the tradeoff between noise and linearity, a new method of harmonic rejection that relaxes gain and phase matching requirements, and a new op amp topology to achieve a wide bandwidth with low power consumption. Furthermore, multiple techniques are introduced to improve the out-of-band and in-band linearity, input matching, and stability. Fabricated in 28-nm CMOS technology, the prototype accommodates channel bandwidths from 200 kHz to 160 MHz and exhibits a noise figure of 2.1–4.42 dB while drawing 23–49 mW. It demonstrates an out-of-band IIP3 of 2.8–9.8 dBm and provides more than 60 dB of rejection for blockers at the third and fifth harmonics of the LO.