分频器
频率合成器
三角积分调变
分流器
倍频器
直接数字合成器
分压器
电子工程
锁相环
师(数学)
威尔金森功分器
中频
计算机科学
电气工程
工程类
无线电频率
功率分配器和定向耦合器
相位噪声
数学
算术
电压
CMOS芯片
作者
Jiaqi Liang,Quan Haiyang,Dianwei Zhang,Li Yang,Yu Xue
出处
期刊:2021 IEEE 5th Information Technology,Networking,Electronic and Automation Control Conference (ITNEC)
日期:2021-10-15
标识
DOI:10.1109/itnec52019.2021.9586973
摘要
The frequency synthesizer is the core component of the radio frequency front end in wireless communication. And the phase-locked frequency synthesizer realizes the signal output of different frequencies by changing the frequency division multiple of the frequency divider. Fractional phase-locked loop can make the frequency synthesizer have higher performance. In this paper, a 32-bit high precision sigma-delta fractional divider is designed in detail from two parts: the programmable divider and the sigma-delta modulator. Finally, the function of the divider is verified by simulation. The working frequency of the decimal divider is 3.55~9.8GHz, the frequency division ratio range is 1~4095, and the frequency accuracy is 0.0235Hz.
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