Study of gate contact over active area

In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress and Hot Carrier Injection stress, we demonstrate that moving the gate contact over active area does not degrade the performances and reliability of studied devices whatever the device area or oxide thickness (down to 2.1nm), and hence, could be a relevant solution in order to reduce the CMOS device area.