A 12.5Gbps dual loop quarter rate CDR using lock detecting technique in 55nm CMOS process

A 12.5Gbps quarter rate SerDes CDR for high speed serial link communication is presented in this paper. The proposed dual loop structure consisting of frequency tracking loop and phase tracking loop has good input jitter rejection. A novel dual switching ppms lock detector is proposed to ensure proper switching of dual loops to prevent false locking. Moreover, a novel quarter rate bang-bang phase detector is designed in phase tracking loop to achieve a low power characteristic. With a clock frequency of 625MHz and the serial received NRZ data at 12.5Gbps, the jitter of the recovered clock is 0.044UI. The power consumption of this CDR is 63.6mW@1.2V.