晶体管
CMOS芯片
材料科学
逻辑门
光电子学
缩放比例
电气工程
工程类
数学
电压
几何学
标识
DOI:10.1109/cstic.2016.7463897
摘要
As the CMOS technology has entered the nanoscale regime, several previously negligible physical effects are becoming increasingly important as a result of aggressive layout scaling. On the other hand, today's IC chips, especially those in the mobile devices with rich functions, need to pack a huge number of transistors into a very small area. In such cases, narrow and small transistors are widely used. As small transistors have both minimum width and minimum gate length, they are more sensitive to the surrounding neighborhood and therefore more susceptible to layout proximity effects than other transistors. In this paper, layout proximity effects (LPEs) of the 28nm Poly/SiON logic technology were studied with a focus on narrow and small transistors. The LPEs include width effect, length of diffusion (LOD) effect, active area spacing effect (ASE), and well proximity effect (WPE). We found that compared with the wider/larger counterparts, the narrow/small transistors exhibited stronger layout dependence effects as expected due to the stronger environment-induced dopant re-distribution and/or stress modulation.
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