A High Speed Adaptive Reflection Cancellation Equalization Circuit with Floating Tap Ffe and Loop-Refactored Dfe for Adc-Dsp-Based Wireline Reciver

High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements.This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture.The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability.The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm.Simulation and FPGA platform validation results demonstrate that at a data rate of 56Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39dB insertion loss(IL).