PCI Express
电缆密封套
足迹
主板
布线(电子设计自动化)
印刷电路板
传统PCI
频道(广播)
嵌入式系统
计算机科学
工程类
计算机网络
计算机硬件
电气工程
电信
现场可编程门阵列
精神科
心肌梗塞
生物
心理学
古生物学
作者
Huafang Ju,Xiang Li,Jimmy Hsu,Shaohua Li,Thonas Su,Mo Liu,Kai Xiao
标识
DOI:10.1109/impact56280.2022.9966709
摘要
PCI-Express (PCIe) data rate continues to double generation by generation from PCIe 4.0 with 16Gbps, PCIe 5.0 with 32Gbps to PCIe 6.0 with 64Gbps in recent years. However, data center motherboard form factor and landing zone requirement remain the same, which implies all enablers in channel need to be improved to meet the maximum board routing length. Because PCB and connector are important components in the platform channel, besides their perspective performance, connector pin field PCB footprint design can also play a big role in channel solution space and PCB cost. In this paper, PCB routing optimization is addressed through the connector footprint optimization and the connector design innovation.
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