A 12bit 160MS/s Pipelined SAR ADC with a MOS Self-Biased Cascoded Ring Amplifier

In this design, a new structure of ring amplifier (RA) is proposed to meet high-speed applications, which uses low threshold voltage transistors to increase the charge rate for capacitors. The stability is ensured by increasing the dead-zone voltage using series-connected transistors. In this design, it is utilized as an inter-stage amplifier in a 160 MS/s, 12 bits pipelined successive approximation (pipeline SAR) analog-to-digital converter (ADC). The pipeline SAR ADC is designed with a 55 nm CMOS process and occupies an overall chip area of 500 × 170 µm ² . Without calibration, the dynamic performance of ADC achieves 58.56 dB for SNDR and 69.14 dB for SFDR.