Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges

Monolithic 3D technology (M3D) is a promising alternative to takle the loss of Moore's Law scaling beyond 22 nm node. By stacking different circuit layers thanks to nano-scale 3D Monolithic Inter Tier Via (MIV), it will be possible to offer a level of circuit integration never reached before, allowing advanced node scaling again as well as mixing heterogeneous technologies. M3D integrates sequentially different layers of transistors, with an ultra-fine pitch, in the 100 nm range, which is 200x smaller than state-of-the-art Through Silicon Vias (TSV) or 50x smaller than Copper to Copper Hybrid bonding (Cu-Cu HB). This high density 3D integration will pave the way towards new architectures, such as neuro- and bio-inspired applications, ultra-high density computing cube and smarter mixed signal devices within low power constraints. This paper presents an overview of M3D technology and potential applications, and in more detail its associated design challenges, respectively on physical implementation aspects and on thermal dissipation.