(Invited) Two-Dimensional Amorphous Carbon Prepared from Solution Precursor As Novel Dielectrics for Nanoelectronics

Low-dimensional electronic materials such as carbon nanotubes, graphene, and transition-metal chalcogenides have drawn a lot of interest from the aspects of both fundamental studies and practical applications. Their atomic-scale thickness and unique electrical properties make them become promising candidates as the drop-in replacement of conventional bulk electronic materials in future electronic devices to enable better performance and enhanced functionality. Research on low-dimensional electronic materials so far has predominantly focused on crystalline semimetals and semiconductors. However, advanced electronic devices also require suitable low-dimensional insulators, which are ideally in the highly disordered amorphous form, similar as SiO 2 for silicon, to avoid the nonuniformity and defects related with grain boundaries, in order to fulfill their potentials. Here we present a new strategy for the solution-based preparation of atomically thin amorphous carbon as a novel 2D insulator. Our unique process can precisely control the film thickness at atomic level and has excellent scalability toward wafer-scale deposition. The obtained 2D amorphous carbon monolayer exhibits mechanical robustness comparable to graphene and can be suspended as a free-standing membrane on transmission-electron-microscopy grid, allowing the structural characterization down to atomic resolution. The structure-property relationship for such amorphous materials at 2D limit was then established based on a combination of experiment and density-functional theory simulation. The unique physical properties of 2D amorphous carbon suggest it as a promising candidate to accompany crystalline low-dimensional semiconductors and semimetals in future nanoelectronic devices, and its performance advantages over conventional 3D metal oxides and polycrystalline 2D insulators were verified in experiment : Serving as the gate dielectric in graphene transistors, the absence of grain boundaries in 2D amorphous carbon allows us to aggressively reduce the gate-dielectric thickness down to merely three-atomic layers to enhance the capacitance coupling between the gate and the channel, while still maintaining a low leakage current density below 10 -4 A/cm 2 , which is many orders of magnitude lower compared to the leakage current across the polycrystalline hexagonal boron nitride with the same thickness. Meanwhile, the perfectly clean van der Waals interface it forms with the graphene channel leads to the sharply reduction of the device hysteresis and thus average effective mobility twice as high as that of devices built with bulk SiO 2 as gate dielectric. Serving as the switching medium in resistive random access memory cells, the atomic-level thinness of the 2D amorphous carbon enables low operating voltage below 0.4 V, fast switching time <20 ns, and low energy consumption per write operation below 20 fJ, together with excellent endurance (>10 4 ) and data retention (>10 years @ 85 o C). Moreover, its atomic structural heterogeneity provides well defined ion-transport pathways as suggested in ab initio simulations, leading to the drastically improved device-to-device and cycle-to-cycle uniformity with the standard deviation of Set/Reset voltages below 50 mV in experiment, which is among the lowest values ever reported for memristors. The concurrent achievement of all these performance metrics has not been accomplished with memristors built on either bulk oxides or polycrystalline 2D materials.