CMOS low-dropout regulator with improved time response

A new configuration of CMOS low-dropout (LDO) regulator is presented. In the proposed regulator a low-output-resistance stage with improved time response is used as an output stage. The analysis of basic parameters together with simulation results are provided to characterize properties of the circuit. The comparison of the new configuration and a know structure using flipped voltage follower (FVF) shows over 100% improvement in suppression of the output voltage undershoot.