Chip Package Interactions: Package effects on copper pillar bump induced BEoL delaminations & associated numerical developments

During the assembly of Flip-Chip devices, some Chip-package compatibility concerns are observed while processing, such as reflow or thermal cycles. In this paper, some illustrations of failed copper pillar bump are presented and the associated failure modes are discussed. In this frame, dedicated numerical methodologies are proposed to take into account these interactions. The difference of scales between interconnects (~1μm), and package (~10 mm) components, the numerous bumps locations as well as the complex copper trace pattern of the substrate induce a large amount of elements and complex modeling. To manage these issues, several methods are used and described: Import of the copper trace pattern from CAD file, homogenization technique, multi-scale technique and dedicated scripts to automatically investigate local stress at all bump locations. Based on an actual product, typical results are depicted to illustrate the added-value of the developed methods. Focus is done on the package parameters such as bump design factors (pitch, rows number and layout) and substrate... Results show that by optimizing the densities and the bump locations with regard to the die, the stress induced by chip-package interactions can be significantly reduced. Pitch, presence of dummies bump or regular layout are underlined as key parameters. Moreover, a detailed analysis of the stress field nearby the bump according to its location with regard to the die is presented. By proposing simulation methodology including whole conception flow, this paper brings added values for product designers whose face mechanical Chip Package Interactions issues.