作者
Hans Mertens,R. Ritzenthaler,Adrian Chasin,T. Schram,E. Kunnen,Andriy Hikavyy,Lars‐Åke Ragnarsson,Harold Dekkers,Toby Hopf,Kurt Wostyn,K. Devriendt,Soon Aik Chew,M. S. Kim,Yoshiaki Kikuchi,Erik Rosseel,G. Mannaert,S. Kubicek,S. Demuynck,A. Dangol,N. Bosman,J. Geypen,Patrick Carolan,H. Bender,K. Barla,N. Horiguchi,D. Mocuta
摘要
We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ~ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.