Design and Verification Flow of Multi-stage Sigma-delta ADC Digital Core

There is a need for analog-to-digital converters with high signal-to-noise ratio and large signal bandwidth to solve a number of radiolocation problems. Developing such ADC is a challenge in analog core, digital core and verification. The design flow of the digital core must take into account possibility of changing the analog core specification at any design stage, provide ability to quickly obtain synthesizable RTL code of the device and conduct its functional verification. Automation tools were used to reduce the time spent on development and verification. This article describes the developed software package that generates synthesizable RTL code and verification environment configurations for each stage of development of the analog core of the multi-stage sigma-delta ADC. Results after functional verification are presented.